1. Field of the Invention
This invention relates to semiconductor devices and, in particular, semiconductor devices suitable for optical communications systems.
2. Art Background
An optical communications system generally includes a source of electromagnetic radiation, a lightguide to transport this electromagnetic radiation, and a detector to detect the electromagnetic radiation as it exits the waveguide. Generally, the detector has been linked to semiconductor devices suitable for processing the detected information through conventional discrete conducting pathways, such as gold strips or wires. The use of these discrete conductors has several disadvantages, such as an associated capacitance which decreases response time. By combining the photodetector with at least a portion of its associated electronic circuitry on a single semiconductor substrate, this capacitance is eliminated. Thus, at present, there is a strong incentive to accomplish this integration.
To produce an integrated structure, the photodetector and the associated electronics are built on an insulating substrate. Fabrication is typically accomplished by sequentially depositing and configuring layers of various materials on the substrate. To prevent device degradation introduced by strain, any crystalline layer in the structure is lattice-matched to the underlying crystallized layer. Since most photodetectors presently contemplated are based on III-V semiconductor materials, the substrate and the associated electronics are conveniently based on similar materials to allow lattice-matching. For example, an iron-doped indium phosphide substrate is overlaid by a lattice-matched buffer region such as an indium aluminum arsenide buffer region. The buffer region is typically sufficiently thick, e.g., 0.1 .mu.m to 1 .mu.m, to eliminate any crystal defects associated with the underlying substrate surface. If the active layer for the overlying electronic devices is to have a different stoichiometry from that of the first buffer layer, then it has been empirically found that a second thin buffer layer with the same stoichiometry as that of the active layer, but with no intentional doping, enhances device properties. The field effect transistor (FET) circuitry and the photodetector are then fabricated by forming and configuring further overlying layers. For example, these layers are formed to produce the essential components of the FET, i.e., (1) a source electrically connected to (2) a drain by (3) an active channel, e.g., a region of n-type doped indium gallium arsenide, and (4) a gate structure that controls the electrical flow through the channel.
In this context, various FET gate configurations have been explored. In one approach, a field effect transistor with a junction gate (JFET) is employed and is fabricated by depositing a semiconductor material such as p-type doped indium gallium arsenide onto the active channel. Currently, this approach allows relatively expeditious fabrication and yields adequate device characteristics such as transconductances up to 100 mS/mm. (Transconductance is defined as the change in source-to-drain current measured in milliamperes effected by a 1-volt change in the gate voltage per millimeter width of active channel.)
However, it is always desirable, by increasing transconductance,to yield the possibility of enhanced speed and greater sensitivity. Other gate configurations have been pursued in an attempt to effect such enhanced characteristics. For example, an insulated gate formed by sequentially depositing onto the active channel a silicon nitride layer and a metal contact has been investigated. To preclude pinhole formation, the silicon nitride must be relatively thick, i.e., 20 nm to 50 nm. However, this thickness requires a higher applied gate voltage to control the electrical current in the channel and thus lowers the achievable device gain. Such a device is further plagued by drifting electrical output due to both electron traps and mobile ions in the insulating layer.
In a second approach, attempts have been made to form an enhanced Schottky barrier gate on the active channel by employing a thinner silicon oxide insulator (thickness of 5 nm to 15 nm). These attempts have produced undesirable gate leakage currents probably due to pinhole formation.
A third gate configuration that theoretically offers enhanced characteristics includes a semiconductor-based dielectric layer, i.e., a low conductivity semiconductor layer with an energy bandgap larger than that of the active channel, and attendant high Schottky barrier height, e.g., an undoped indium aluminum arsenide layer, and a metal contact. Despite theoretical predictions, these devices also suffer from high gate leakage current, e.g., leakage current greater than 6 amps/cm.sup.2.